Field
The disclosure relates generally to a buck voltage regulator and, more particularly, to a buck voltage converter operating in pulse frequency modulation (PFM) mode thereof.
Description of the Related Art
Voltage regulation is important where circuits are sensitive to transients, noise and other types of disturbances. The control of the regulated voltage over variations in both semiconductor process variation, and temperature is key to many applications. Additionally, the noise generation from switching noise emissions from inductors can impact sensitive circuitry and lead to system level issues in real systems, and applications. Electromagnetic interference (EMI) is a growing concern in electronic components and systems.
EMI is a concern in voltage converter circuitry for buck, boost, and buck-boost converters, and more particularly for circuitry operating in pulse frequency modulation (PFM) mode. The PFM mode of operation is commonly used in “sleep mode” in direct current-to-direct current (DC-to-DC) converters. Buck converters can operate in two modes, known as pulse frequency modulation (PFM) mode, and pulse width modulation (PWM) mode. The PFM mode is typically used for low load currents. In a buck converter output driver stage, there is typically a p-channel metal oxide semiconductor (PMOS) transistor pull-up device, and an n-channel metal oxide semiconductor (NMOS) transistor pull-down device. In PFM mode of operation, the buck converter turns on the PMOS transistor when the output voltage falls below the digital-to-analog converter (DAC) voltage. In the buck converter, the PMOS transistor is then turned off when the current in the inductor coil reaches a threshold value (e.g., the “sleep current limit”). The NMOS is turned on when the PMOS is turned off. The NMOS is then turned off when the current in the coil is fully discharged. PFM is not typically used for large currents as the current limit is normally set low to maximize efficiency.
FIG. 1 shows a circuit schematic block diagram of a buck control system for pulse frequency mode (PFM) sleep mode. The buck 100 is composed of a power supply VDD 101, and ground VSS 102. The output driver stage comprises a PMOS pull-up transistor 105 and NMOS pull-down transistor 110. The PMOS transistor 105 has a gate driver 115 and the NMOS transistor 110 has a gate driver 120. The gate drivers are driven by a control logic block 125 which receives signals Vunder 126 and Ilimit 127. The output stage of the PMOS transistor 105 and the NMOS transistor 110 provides current to inductor Lout 150, with the current sensed by sense circuit 130. The sense circuit 130 provides a feedback signal line 132 for the Ilimit signal flag 127, based on a current limit reference Ilimit_ref provided by current source 135. Voltage LX 140 connected at the input to inductor Lout 150, connected to output capacitor 155 and output signal Vout 160. The output of the pass devices 105 and 110 are connected directly to the LX node 140. The sense block detects the current flowing through the LX; this outputs a scaled replica of this output current to the reference current source 135. If the sensed current is higher than the reference current, the voltage at node 132 will fly high and be detected by the control block 125. The output signal Vout 160 is connected to the feedback loop 165 configured to provide the signal Vfb 171 to comparator 170. A digital-to-analog converter (DAC) 175 is configured to provide a signal Vdac 173 to the comparator 170. When the output voltage falls below the DAC voltage 173 the Vunder signal 126 is raised. This turns on the PMOS transistor 105 which charges up the current in the inductor coil 150. When the inductor coil current reaches the current limit, the Ilimit flag 127 is raised. This turns off the PMOS transistor 105 and turns on the NMOS transistor 110. Once the inductor coil current reaches zero, the NMOS transistor 110 turns off, and the output goes high-impedance. The cycle is started again once the output voltage again falls below the DAC voltage 173.
FIG. 2 shows the timing diagram 200 for the signals for this mode of operation. The feedback voltage Vfb 210 and digital-to-analog converter output voltage Vdac 220 are overlaid in the timing diagram 200. The comparator output signal Vunder 230 is shown below highlighting the transitions associated with the comparator input signals. FIG. 2 shows the p-channel MOS (PMOS) gate signal Pgate 240, n-channel MOS (NMOS) gate signal N gate 250 as well as the current limit signal Ilimit 260 and inductor coil current Icoil 270.
The feedback voltage Vfb 171 is equal to the output voltage of the buck converter 160. As this falls below the digital-to-analog converter (DAC) voltage Vdac 173 the under-voltage signal Vunder 126 turns on. This leads to the turn on of the PMOS gate (active low), which causes the inductor coil current to increase. Once this reaches the current limit, the PMOS 105 turns off and the NMOS 110 turns on. The inductor coil current then discharges. Once this is fully discharged, the NMOS 110 is turned off. The output voltage 160 then discharges with the applied load until the feedback voltage Vfb 171 once again falls below the DAC voltage Vdac 173.
As the load increases so the frequency with which the buck converter switches also increases. The frequency of the buck converter can vary from very low frequencies (less than 1 Hz) up to the maximum frequency of the buck converter, determined by minimum on time and minimum off time. This can be typically around 5 MHz.
The change in current in the coil of the buck tends to emit noise which is picked up by surrounding circuits. This noise can be the source of issues within real systems and applications. Electromagnetic interference (EMI) can lead to both soft failures and hard failure. Soft failures can include timing impact, false signals, and system disturbs. Hard failure can be damage to internal devices or components that are destructive.
U.S. Patent Application 20140111174 to Shtargot et al describes a switching regulator with a split inductor for reduction of electromagnetic interference (EMI).
U.S. Patent Application 20130051089 to Pan et al., describes a frequency jittering control circuit for a PFM power supply includes a pulse frequency modulator to generate a frequency jittering control signal to switch a power switch to generate an output voltage. The frequency jittering control circuit jitters an input signal or an on-time or off-time of the pulse frequency modulator to jitter the switching frequency of the power switch to thereby improve EMI issue.
U.S. Pat. No. 7,893,663 to Ng, describes a method and apparatus for active power factor correction with sensing the line voltage. This utilizes a power factor correction apparatus which uses Pulse Frequency Modulation (PFM) to control an AC/DC converter. The switching frequency varies with the line voltage such that the converter emulates a resistive load. By using PFM control, EMI is spread over a range rather than concentrated at a few frequencies
U.S. Pat. No. 6,204,649 to Roman describes using a switching regulator for reducing electromagnetic interference (EMI) includes a PWM controller which incorporates a varying frequency oscillator for controlling the operating frequency of the switching regulator.
In these prior art embodiments, the solution to establish a switching regulator with reduced EMI utilized various alternative solutions.